As is known in the art, as monolithic microwave integrated circuits (MMICs) are designed to operate at ever higher frequencies, the effects of dielectric loading on various MMIC conduction paths (including gates and transmission lines) becomes more pronounced. The minimization of such loading is critical to achieving the desired gain performance.
As is also known in the art, plasma enhanced chemical vapor deposition (PECVD) is widely used for the deposition of silicon nitride, which may act as a passivation layer to passivate components, or act as a capacitor dielectric. This deposition technique however, coats regions of the MMIC where the presence of additional dielectric is not desired and adversely impacts device performance at the higher frequencies.
As described in co-pending patent application Ser. No. 13/849,858, filed Mar. 25, 2013, published in U. S. Patent Application Publication 2014/0284661, published Sep. 25, 2014, assigned to the same assignee as the present patent application, a method was disclosed for forming a semiconductor structure, the entire subject matter thereof being incorporated herein by reference. The method included: providing a semiconductor layer with a transistor device having a control electrode for controlling a flow of carriers between a first electrode and a second electrode; depositing a passivation layer over the first electrode, the second electrode and the control electrode; depositing an etch stop layer on the passivation layer, such etch stop layer being disposed over the control electrode; forming a dielectric layer over the etch stop layer; and etching a window through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode.
In forming such structure it was discovered that chemicals used in the photolithographic processing effected the etch stop layer.
In accordance with this disclosure, the etch stop layer is formed as a composite structure, comprising: a first etch stop layer on the passivation layer, a buffer layer on the first etch stop layer, and a second etch stop layer on the buffer layer. With such an arrangement, chemicals used in the photolithographic processing while effecting the second etch stop layer are prevented from effecting the first etch stop layer by the buffer layer.
More particularly, it was found that the etch stop layer described in the above referenced U. S. Patent Application Publication 2014/0284661 was subject to attack from other commonly used process chemicals in standard MMIC fabrication such as ammonia and photoresist developer. Employing a buffer, such as, for example, a silicon dioxide interlayer, effectively creates a double-selective etch-stop layer that survives typical MMIC fabrication processing up to the point where etch-back is required. Post etch-back, it has been found that the residual etch stop material can be removed by timed exposure to ammonia since ammonia acts as a highly selective etchant to Atomic Layer Deposition (ALD) deposited aluminum oxide to PECVD nitride. This removal mitigates impact to RF performance of any residual dielectric associated with the etch-stop layer.
In one embodiment, the first etch stop layer is aluminum oxide.
In one embodiment the buffer layer is silicon dioxide;
In one embodiment, the second etch stop layer is aluminum oxide.
In one embodiment, the transistor device is a field effect transistor.
In one embodiment, the semiconductor layer is a III-V semiconductor material.
In one embodiment, the passivation layer is silicon nitride.
In one embodiment, the dielectric layer is silicon nitride.
In one embodiment, the dielectric layer is Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride
In one embodiment, the first etch stop layer is an atomic layer deposited (ALD) layer.
In one embodiment, the second etch stop layer is an atomic layer deposited (ALD) layer.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.